The present application claims priority to currently pending United Kingdom Patent Application number 0119014.9, filed on Aug. 3, 2001.
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The present subject matter generally relates to a frequency doubler circuit arrangement. More particularly, the disclosed technology concerns a frequency doubler circuit arrangement that reduces the number of voltage controlled oscillator modules needed for device operation at multiple frequency bands.
It is common now for cellular telephones to have the capability to operate at multiple frequency bands, typically one band being at around 900 MHz and another at around 1800-1900 MHz. It is common to provide such telephones with a frequency doubler circuit, in order to reduce the number of voltage controlled oscillator (VCO) modules required (a 900 MHz source is doubled up to 1800 MHz).
A known frequency doubler circuit includes a non-linear diode circuit, which generates harmonics of an input signal, one of the harmonics being at twice the frequency of the input signal. However, such circuits are not power efficient, and require significant amounts of filtering to isolate the required harmonic.
Another known circuit is shown schematically in FIG. 1. Referring to FIG. 1, the frequency doubler circuit 10 comprises an input terminal 11, to which is applied an RF signal, a phase shift circuit 12, a mixer 13, a band pass filter 14 and an output terminal 15. The phase shifter circuit 12 produces in-phase and quadrature versions of the input signal, which are supplied to two different signal inputs of the mixer 13. The output of the mixer contains a signal having twice the frequency of the input signal, which is then passed by the filter 14 whereas signals of other frequencies are blocked by it. The need for a phase shift circuit is considered to be disadvantageous, and most implementations also require limiting amplifiers to generate the quadrature drive signals.
A third known frequency doubler circuit is shown schematically in FIG. 2. Referring to FIG. 2, the circuit 20 comprises a pair of bipolar transistors 21, 22, which have their emitter electrodes connected to ground 23 via a resistor 24. The collector electrodes of the transistors 21, 22 are connected together and, via a passive filter load comprising an inductor 25, a capacitor 26 and a resistor 27, to a positive supply terminal 28. A differential input signal is applied to input terminals 29, 30, which are connected to the base electrodes at the transistors 21, 22 respectively, and a single-ended output is provided at an output terminal 31, which is connected to the collectors of the transistors. The transistors 21, 22 effect full-wave rectification of the input signal, with the result being filtered by the filter load 25, 26, 27. As well as not delivering good power conversion efficiency, a single-ended output is provided, whereas differential outputs are usually preferred.
Objects and advantages of the disclosed technology will be set forth in part in the following description, or may be obvious from the description, or may be learned through practice of the technology. The present subject matter recognizes and addresses various drawbacks and other shortcomings related to frequency doubler circuits. Thus, it is a principal object of the presently disclosed technology to provide a frequency doubler circuit, which when utilized in certain electronic devices reduces the number of voltage controlled oscillators (VCOs) that are needed for effective operation of such devices.
It is a further principal object of the present subject matter to provide a frequency doubler circuit arrangement having a differential output and good rejection of the frequency of selected input signals.
Exemplary embodiments of the disclosed technology generally provide for a frequency doubler circuit comprising a full wave rectifier circuit, a biased transistor circuit, and output terminals of the respective full wave rectifier and biased transistor circuits. The full wave rectifier circuit preferably has an input forming an input of the overall frequency doubler circuit and also a first terminal connected to a first supply terminal via a first current source. The biased transistor preferably has a first terminal connected to the first supply terminal via a second current source and also connected to the first terminal of the rectifier circuit. The output terminals of the rectifier circuit and the biased transistor circuit preferably form differential output terminals of the frequency doubler circuit arrangement.
Such exemplary frequency doubler circuits may incorporate other features and elements or combinations of other features and elements to form still further exemplary frequency doubler circuit embodiments. For instance, the first terminal of the biased transistor circuit and the first terminal of the rectifier circuit may be connected via a capacitor. The outputs of the rectifier and biased transistor circuits may be connected to a second supply terminal via a filter load, for example, an inductance-capacitance-resistance filter. The first and second current sources may be substantially constant current sources, such as those formed of transistor-based current mirror circuits.
Alternative embodiments of the disclosed technology provide for radiotelephone devices that comprise at least one voltage controlled oscillator (VCO) and a frequency doubler circuit that enables a single VCO to be employed for providing signal sources at more than one operating frequency. The frequency doubler circuit of such an exemplary such radiotelephone device preferably comprises a full wave rectifier circuit and a biased transistor circuit. Output terminals of the respective full wave rectifier and biased transistor circuits preferably form differential output terminals of the frequency doubler circuit arrangement. The full wave rectifier circuit preferably has an input forming an input of the overall frequency doubler circuit and also a first terminal connected to a first supply terminal via a first current source. The biased transistor may have a first terminal connected to the first supply terminal via a second current source and also connected to the first terminal of the rectifier circuit by a capacitor. The outputs of the rectifier circuit and the biased transistor circuit are preferably connected to a second supply terminal via a filter load.
Additional objects and advantages of the presently disclosed technology will be set forth in part in the description that follows, and in part will be obvious through the description, or may be learned by practice of the technology. The objects and advantages of the present subject matter may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate at least one presently preferred embodiment of the technology as well as some alternative embodiments. These drawings, together with the description, serve to explain the principles of the present subject matter but by no means are intended to be exhaustive of all of the possible manifestations of the disclosed technology.